This invention relates to transistor circuits, and particularly to a circuit for reducing the gate leakage current of a junction field effect transistor, or JFET.
A pair of matched junction field effect transistors are often advantageously utilized as the input stage of an operational amplifier since two ideal requirements for such an amplifier are infinite input impedance and zero input current. It is well known that field effect transistors have an extremely high input impedance and thus are practical for operational amplifier use. Morever, in an ideal JFET, there should normally be no input, or gate current since the diode junctions which comprise the transistor are reverse-biased. In practice, however, reverse-biased pn junctions have a small leakage current, and therefore a finite input current will exist at the gate input of the JFET. This gate leakage current is relatively small at room temperature, but can become quite large at higher ambient temperatures. A high gate leakage current is undesirable when viewed in conjunction with the need for zero input current in the ideal operational amplifier.
It is known in the prior art to provide a cancellation circuit to compensate for gate leakage current in a JFET. Such a circuit is described in U.S. Pat. No. 4,068,254 to Erdi. In this patent, means are provided for establishing a reference current, the magnitude of which is a function of the JFET's gate leakage current over a given operating range. A proportional current mirror tracks the reference current to yield a current which is substantially equal in magnitude to the gate leakage current. This current is applied to the gate of the JFET to effectively cancel the JFET input current that would otherwise be required to supply the gate leakage current. This circuit has proven satisfactory but does not provide low enough bias currents for precision operational amplifier applications.